Microelectronic devices are fabricated on a semiconductor substrate as integrated circuits in which various conductive layers are interconnected with one another to permit electronic signals to propagate within the device. An example of such a device is a complementary metal-oxide-semiconductor (CMOS) field effect transistor (FET) or MOSFET.
An exemplary FET or MOSFET includes a gate electrode on a gate dielectric layer on a surface of a silicon substrate. However, as CMOS technology is continuously miniaturized and the transistor count exponentially rises, overall power consumption is also increased, making performance per watt of energy consumption a key figure-of-merit for today's performance microprocessors. Narrow gap semiconductor-based materials such as Ge and III-V devices could enable the next generation of logic transistors operating below 0.5 V supply voltages as these materials have excellent low-field and high-field electron transport properties, thereby resulting in high-speed switching under low operating electric fields. Further scaling of tri-gate MOSFETs with new channel materials requires scaling of high-k/metal gate stacks with inversion layer thickness (Tinv) below 1.3 nm. However, current gate stack materials do not meet these requirements for Tinv.
Therefore, there is a need for new materials for the gate stack of Ge and III-V channel transistors, as well as methods and apparatus for forming such layers.